AI Develops New Computer Chips in Record Time
It usually takes several months – sometimes even years – to develop new computer chips. A new AI from Google Research has now relieved chip designers of this task and does it in just six hours.
Mountain View (U.S.A.). As the tasks of chip design become more and more complex, the development teams have to invest more and more time in tedious calculations. Not only does this take a long time, it also increases the cost of the chips. But now researchers have developed an automated method based on machine learning and presented it in the journal Nature. Initial tests show that these self-learning algorithms can design a sophisticated chip architecture in just six hours.
Computer chips are essentially circuits that process information according to their design. The way an electronic circuit is designed determines its processing power, energy efficiency, price, and a number of other important properties. Researchers at Google have developed a new technology for the design of computer chips in an artificial intelligence (AI) laboratory, with which they can develop new and highly efficient computer chips in just a few hours.
“Our method automatically generates chip floor plans that are comparable or even better than man-made ones in all key functions: from energy consumption to performance and the size of the chip,” explains Azalia Mirhoseini from Google Research.
AI values performance parameters
This is made possible by an algorithm that virtually and independently arranges the individual blocks of a chip and estimates the resulting performance parameters. In a very short time he compares thousands of different floor plans. At the same time, this algorithm learns which organization strategies and floor plan layouts are particularly advantageous for computing power as well as energy and space requirements.
The chips are messy but powerful
The performance of the apparently chaotic layout of the algorithm is astonishing. This success is easy to understand because the chip delivers the same quality while saving valuable development time. This new approach should soon make it easier for developers to cope with the increasingly demanding task of designing complex floor plans for increasingly powerful computer chips.