IBM Tests 2-Nanometer Chips

On the first 2 nm chip manufactured, IBM packs twice as many transistors as on previous 5 nm semiconductor elements: 333 million per square millimeter.

IBM‘s research department has produced the first semiconductor component with structure widths of 2 nanometers on a pilot system, i.e. technology of the next but one generation. 5 nm chips are currently in series production, followed by the 3 nm generation. Several years will pass before the serial production of 2 nm chips.

Graphics chips and x86 processors from AMD and Intel have so far at best run off the assembly line with 7 nm technology, such as AMD’s Ryzen 5000 CPUs at the chip contract manufacturer TSMC. The latter also already produces 5-nm chips such as Apple A14 and M1 as well as Qualcomm Snapdragon 888. According to IBM’s announcement, 2-nm transistors with the same power consumption should provide 45 percent more performance than the best 7-nm transistors or 75 with the same performance Convert percent less energy.

Lots of transistors
Unfortunately, the chip manufacturer’s nanometer specifications have long since ceased to describe specific structure widths, but are class names for the continuous reduction in size of the transistors. According to its own information, IBM’s 2-nm technology squeezes 50 billion transistors onto a chip area the size of a fingernail. The Anandtech website has found out that this means a size of 150 mm² – accordingly, in the best case, around 333 million transistors fit on every square millimeter of silicon. This ideal value usually relates to particularly densely packed 6T SRAM cells, each made up of six transistors (6T). Transistors for other functions such as logic or analog blocks are often larger.

For comparison: Wikichip has analyzed various 7 nm semiconductor elements and came up with up to 91 million transistors / mm² at TSMC and 95 million at Samsung. Chips produced at TSMC with 5 nm structures, such as Apple’s M1 processor, are estimated to have between 130 and 230 million transistors / mm². With more densely packed and more efficient manufacturing processes, for example, faster processors and graphics cards can be built.

IBM uses a form of “Gate All-Around” (ATM) technology to build the transistors, known as nanosheets in the company. The conductive channel of the field effect transistor (FET) is surrounded on all sides by the gate electrode in GAA-FETs. TSMC wants to use similar technology from its own 2 nm generation, Samsung from the step to 3 nm.

Research project
So far, the 2-nm technology from IBM has been a development project. Series production of 2 nm processors would not be realistic until 2025 at the earliest in cooperation with Samsung or Intel. IBM has a research alliance with Samsung and Globalfoundries, but Globalfoundries is out of the race for the most modern manufacturing processes. The partnership with Intel is still in its infancy.

In 2017, IBM already showed the first 5 nm chip with ATM transistors. Four years later, however, the Power10 server CPU with 7 nm structures from Samsung appears – IBM is later in this generation than competing companies such as AMD and Nvidia.